The present invention relates to a pulse circuit of a magnetic disk apparatus, which converts a peak position of a read signal from a magnetic head to a pulse signal serving as a digital signal.
In general, the data read operation in a magnetic disk apparatus is performed by a readout circuit which includes a pulse circuit. FIG. 1 illustrates a typical readout circuit. Data recorded on a magnetic disk is detected by a magnetic head 1 and is produced as a read signal (head reproduction signal) of an analog signal (voltage signal). The read signal is then amplified by a pre-amp 3, and head noise, ambient noise and circuit noise of the amplified read signal are removed by a low-pass filter (LPF) 5. The filtered signal is differentiated by a differentiator 7. The differential signal is then quantized by a signal detector. Finally, the quantized (or digital) signal is supplied as read data to a controller of the magnetic disk apparatus.
The signal detector (mentioned above) is used to convert a peak position of the read signal to a pulse signal (which serves as a digital signal) and as such is essential to the stable reading of data. In the typical signal detector, an analog signal (differential signal) c obtained by differentiating the read signal is supplied to one input terminal of a comparator 11. A signal having a phase opposite to that of the differential signal c is supplied to the other input terminal thereof. A signal a, having a phase opposite to that of the read signal, is applied to comparator 13. the comparator 13 generates a pulse signal b which rises when the read signal a exceeds a predetermined voltage level TH+ and which falls when the read signal a is less than the predetermined voltage level TH-.
The pulse signal b is supplied to a delay line 17 through an inverter 15 and is delayed by the delay line 17 for a predetermined delay time. This delayed signal is inverted by an inverter 19, which produces a signal e. The signal e is supplied to a data input terminal D of a D-type flip-flop 21. In FIG. 1, reference numerals R1, R2 and R3 denote resistors and reference symbols +V and -V denote voltages.
The comparator 11 produces pulse signals d and f, which rise and fall in response to a zero-crossing of the differential signal c, as shown in FIGS. 2E and 2G, respectively. Pulse signal f is an inverted signal of pulse signal d. The differential signal c is obtained by delaying, for a given delay time, an analog signal c' (see FIG. 2C) which has zero-crossing points respectively corresponding to the positive and negative peaks of the read signal a, thus representing the differentiated read signal. Pulse signal d is supplied to one input terminal of NAND gate 23, and pulse signal f is supplied to one input terminal of NAND gate 25. An output (Q output of FIG. 2I) signal h from the flip-flop 21 is supplied to the other input terminal of NAND gate 23, and an output (Q output of FIG. 2H) signal g from the flip-flop 21 is supplied to the other input terminal of NAND gate 25. The output signals from NAND gates 23 and 25 are supplied to NAND gate 27.
An output signal i (FIG. 2J) from NAND gate 27 is supplied as a clock signal to a clock input terminal CLK of the flip-flop 21. The flip-flop 21 supplies output signals g and h (also discussed above) to a logic circuit 29 (FIG. 1) in synchronism with the clock signal i. The logic circuit 29 generates a pulse signal j having the waveform shown in FIG. 2K (i.e., the digital signal representing the zero-crossing points of the differential signal c which correspond to the peaks of the read signal a). The pulse signal j is regarded as the above-mentioned read data. The logic circuit 29 is constituted by inverters 31, 33 and 35, NAND gates 37, 39 and 41, a delay line 43, and so on.
The pulse circuit having the configuration described above produces a conversion of the read data from the magnetic head to a digital signal. However, according to the conventional system described above, unnecessary zero-crossing points x occur in the differential signal c, as shown in FIG. 2D. Unnecessary pulse signals Px occur in the output signals d, f from the comparator 11. For this reason, a pulse signal i having an insufficient pulse width is often supplied, as the clock signal, to the flip-flop 21. Subsequently, a race condition occurs in the flip-flop 21, and output signals g and h become unstable. These unstable signals increase the error rate and degrade reliability of the magnetic disk apparatus.